1. Field of the Invention
The present invention relates to a semiconductor device, and its fabrication method, and more particularly, to a semiconductor device, and its fabrication method, having an improved operating performance.
2. Description of the Prior Art
With reference to FIG. 1, a brief description of a conventional CMOS device is as follows.
The conventional CMOS device includes a semiconductor substrate 11 having an N-type metal oxide NMOS region and a P-type metal oxide PMOS region. A field region 12 is formed between the NMOS region and the PMOS region. The field region 12 separates and distinguishes the NMOS region from the PMOS region.
An NMOS device and a PMOS device are also formed on the NMOS and PMOS regions, respectively. The NMOS and PMOS devices include an NMOS gate structure 100a and a PMOS gate structure 100b, respectively. The NMOS and PMOS gate structures 100a and 100b include gate insulating film 13 formed on a portion of the NMOS and PMOS regions, respectively, gate electrodes 14 formed on the gate insulating film 13, and a gate cap insulating film 20 formed on the gate electrodes 14. The NMOS and PMOS gate structures 100a and 100b also include sidewalls 19 formed on each side of the gate insulating film 13, the gate electrodes 14, and the gate cap insulating film 20.
In the NMOS region on each side of the NMOS gate structure 100a are formed n.sup.+ source and drain (S/D) regions 16 (high density N-type impurity source and drain regions). Adjacent to each of the n.sup.- S/D regions 16 and under the NMOS gate structure 100a are formed n.sup.- low density (LD) regions 15 (low density N-type impurity regions). In addition, in the PMOS region on each side of the PMOS gate structure 100b are formed p.sup.- source and drain (S/D) regions 18 (high density P-type impurity source and drain regions), and p.sup.- low density (LD) regions 17 (low density P-type impurity regions) are formed adjacent to each of the p.sup.- S/D regions 18 under the gate structure 100b.
The conventional CMOS device, as described above, has the following problems. It is difficult to improve device performance when the sidewall length (i.e., the PMOS device are identical. The current driving capability can be improved for the NMOS device by decreasing the sidewall length of the sidewalls 19 for the NMOS device. Decreasing the sidewall length decreases a channel length between the n.sup.- LD regions 15 of the NMOS device and decreases the length of the channel between the p LD regions 17 for the PMOS device.
The decreased channel length improves the current driving capability for the NMOS device. However, because P-type impurity diffusion has a greater influence than N-type impurity diffusion, decreasing the sidewall length for the PMOS device causes the p.sup.- S/D regions 18 to increase in the vertical direction, i.e., to deepen, and to decrease the thickness of the and the p.sup.- LD regions 17. As a result, decreasing the sidewall length of the sidewalls 19 for the PMOS device deteriorates the short channel property for the PMOS device.